AES in Verilog

Hear from our mistakes and learn how to prevent setbacks while also getting ideas for how to go above and beyond our work.

Goals

Here is a link to our project proposal. The project proposal includes an description of the project, MVP, planned goals, strectch goals, and a work plan.
Our MVP included:

1. Inputing a text string and encoding it into hex (compare premade Python library binascii and code written by our team)
2. Come up with a good cipher (cryptographic algorithm) to encrypt our data
3. Create block diagram of how the encryption works and how all the pieces fit together
4. Accurately portray how information travels through the encryption process
5. Implement AES data encryption in high level verilog module
6. Implement decryption of encrypted information in high level verilog module.

1. Optimize for speed - Our encryption and decryption run faster than python

We realized that anything that is implemented in Verilog will inhertly be faster than Python because Verilog is a hardware implementation.

We have successfully completed every item on this list and achieved both our MVP and planned goal. With respect to the work plan, we underestimated how long it would take to fully understand and implement everything. Therefore, we didn't not have time to pursue our stretch goals which are listed below.

Stretch Goals:
1. Some form of this functional on FPGA board
2. Some sort of GUI with encryption and decryption options: Encrypt - takes user text input and key input, Decrypt - takes key input - if correct, returns decrypted text, if not returns results of decryption with incorrect key (will be nonsense)
3. Explore non-symmetric-key algorithms: asymmetric, hashing, etc.
4. Modules communicating with python program

Challenges

Our biggest challenge was implementing mix columns in diffusion. The resources that we had been working with implied that this could be done through matrix multiplication. However, after the code that we wrote for matrix multiplication did not give the right answer, we dug deeper. As it turns out, the matrix multiplication that is done in AES involves a different type of math: Galois finite field arithmetic. We researched this for awhile and consulted with our NINJAs, and eventually found look up tables giving values for multiplication in the field G(2^8). We then implemented the matrix multiplaction using this for the multiplication and XOR for the addition. This obstacle was overcome thru sheer persistence.

Some smaller obstacles we faced were mainly verilog troubles. It took us a while to figure out how to implement SystemVerilog features in our code, and to set up our development enviroment to allow the running of SystemVerilog code. We also encountered many small verilog errors relating to things like port size and reg to wire errors. These smaller obstacles were overcome thru simple debugging.

Triumphs

The most exciting part of our project was when we first got encryption working. We used an online AES Encryption Generator and entered in a simple message and key to get the encryption. Then we entered the same message and key into our Verilog implementation. We wrote the online generator on a whiteboard. As we started reading out the output of our implementation, it matched! This was when we first realized that we had successfully implemented AES encryption in Verilog.

Moving Forward

For our initial project proposal, we set ourselves a few reach goals.

1. Port our code onto an FPGA board
2. Create a GUI that allows a user to enter in a text input and key input