AES in Verilog

Home What is AES? Instructions Schematics Reflection Meet the Team

For our final project in Computer Architecture, we implemented Advanced Encryption Standard (AES) in Verilog.

See our code on GitHub!


Why did we choose to do AES?
All the members on our team were very interested in cryptography and being secrect agents therefore we decided on implementing an encrypting and decrypting algorithm in verilog. AES is the most widely adapted cryptography algorithm in the modern world. AES performs well on a wide variety of hardware, from 8-bit smart cards to high-performance computers.
It is very high speed but requires very low RAM.


Resources

  • Federal Information Processing Standards Publication Announcing AES
  • A Stick Figure Guide to AES
  • AES Encryption Generator
  • A Hardware Implementation of AES Using SystemVerilog
  • Tech Target: Search Security: AES definition
  • ASCII Table
  • Python binascii Documentation
  • Python Cryptography Toolkit (pycrypto) Documentation
  • Python’s binascii – hexlify() and unhexlify()
  • Stack Overflow: Define a 2D array in Verilog, a 4x4 matrix
  • Wikipedia: AES
  • Wikipedia: Rijndael mix columns
  • Wikipedia: S-box

An Overview of Our Project

For our final project in Computer Architecture, we implemented Advanced Encryption Standard (AES) in Verilog. To find out more about AES, please go through the resources on the left. We hope you enjoy reading about our project! Our source code can be found on here on GitHub.

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